The H-bridge described in this write-up is capable of currents up to about 40A at 24V, but requires the assembly of a PCB. The mosfets are used as switches and are activated in diagonal pairs. If the voltage reversals are at a high enough frequency, the cycling is unnoticeable. Generally 20kHz is a good choice for PWM frequency because it is well beyond of the dynamic range of motors and just beyond the range of human hearing.
While the concept of a high current H-bridge is fairly simple, many practical considerations complicate implementation. The example H-bridge above works with a 24V supply and all of the specified components. If you need to change a component, it is very likely that the other components will need to be re-sized.
Some rules-of-thumb for each component are provided below. To prevent the noise from having a deleterious effect on the mosfets, there is significant capacitance in close proximity to the mosfets. The diodes that often come integrated into the mosfets also play an important role here. This spike can dissipate by drawing current through the diodes in mosfets 1 and 3, effectively sending the current into the capacitors and battery. It is also possible to reduce the inductive voltage spikes by increasing the time it takes to transition between states.
This can be accomplished by increasing the Gate Resistance covered later. It is important to ensure that the two mosfets on the same half-bridge are never on at the same time.
The IR half bridge driver chip contains logic to prevent this condition from occurring. It outputs the PWM signal to the high mosfet gate while sending an inverted version of the signal to the low mosfet gate.
To be certain that shoot through does not occur during the transient, it also adds a ns dead time where both signals are low. In our example this means that when the high mosfet is turned on the voltage at the source pin the high side of the motor is 24V so the voltage at the gate must be about 34V. The half-bridge driver chip is able to supply this high voltage by using a bootstrapping circuit. The bootstrapping method for achieving the high mosfet gate voltages avoids the need for an additional DC to DC power supply, but for the bootstrapping to work, there needs to be time to recharge the bootstrapping capacitor.
Gate charge can be found on the data sheet and is usually in the units of nanocoulombs nC. To calculate the turn-on and off times we need to know a couple of things: how high the gate-voltage needs to be and how fast the drive circuitry can charge and discharge the gate-capacitance. It is usually specified in the form of a chart like this this is from Wikipedia :. As you can see, for relatively low drain-currents Y axis the FET operates as a small resistance the curve is linear and goes through the origin.
For high currents however, the FET transitions into so-called saturation where the current is pretty much constant. So, if you know the maximum current the FET which is the current limit of the bridge , you can figure out the minimum gate-voltage that is needed to keep the FET linear.
The same diagram for this particular FET looks like this. You see that if the gate voltage V gs is only three volts, the FET would not even be able to conduct 20A.
It saturates at around 15A. With a gate voltage of 3. If you however increase the gate voltage to about 4. So, for our case, we would need a gate voltage of at least 4. In order to turn the same FET off, we need to lower the gate voltage below the so-called threshold voltage.
Driver characteristics are usually quite complex, and they are specified using charts, like this:. Here you see how the output current changes as the function of the output voltage, or the more useful way of looking at it: if you want to draw a certain amount of current out of the pin, how much the output voltage will deviate from its ideal value. This particular chart is from TI and specifies their AHC-series logic output characteristics page To approximate these curves, we can use a very simple model again, using the MOSFET terminology : The output is in saturation mode for high currents — effectively acting as a current-source — and as the current decreases, it transitions into a linear region where it acts as a resistor.
Graphically, we approximate the curve with two lines:. It is typical that an output stage has a somewhat weaker high-side driver, being a P-MOS device. In many cases you can even further simplify the picture and assume either only the current-source or the linear region. So, in theory it can be driven directly by a 5V digital pin.
The constant current approach works the following way: we try to charge up a capacitor with a constant current source to at least a certain voltage. That will take some time:.
The constant resistor approximation is more complex, because of the exponential response of the RC circuit. The turn-on time will be the following:. Both are actually under-estimating the times: the constant current approach will assume more current than the driver can actually deliver at low output voltage drops, while the constant resistance approach at least the way I did it here over-estimates the current for the saturated region. A more precise estimate can be made by combining the two methods, and assume constant current charge and discharge until the knee-point 2.
These calculations can be done for P-channel MOSFETs and drivers as well, but of course you have to slightly change the equations to accommodate for the negative gate-source voltage of those devices. So far so good, we have several ways now to calculate the transient times, with various accuracy.
What tools do you have to influence these numbers? If you want to make the time shorter, your pretty much have two choices: either change the FET to one with a lower gate capacitance or you change the driver to one that can provide more current. If you want to make the time longer, you have more options. One thing you can do is to add more capacitance to the gate by adding an extra capacitor towards ground for example.
By far the most common way of controlling the trun-on and —off times is to add a series resistor to the driver outputs:. The series resistor method is ineffective if the driver is truly a current source, but that very rarely is the case.
Normally, the effect is two-fold: one is that by requiring more voltage for the same current it gets the driver faster out of its current source region into it linear region. Note that if you do the same calculations for t off , you usually get a different R g value.
So the time it takes to get out of the current-source region is this:. After that time, the driver is in its linear constant resistance mode, so the previous equations can be used. The total turn-on and —off times for this approximation are the following:.
After all this math you might ask this question. The reasons you might want to lower the transients are the following:. My guideline is that I try to keep the transient times to around 0. This means that for a 20kHz bridge, I like to see ns transient times.
In the following I will only deal with one-half of the bridge. On the low-side, we only have one type of device to deal with: N-channel FETs. These need a low voltage to turn them off, and a higher voltage typically in the 5…15V range to turn them fully on. The question is: what to put in the place of the mystery circuit:. For very simple, low-voltage designs, they might be completely missing, and the FETs are directly driven by logic level signals.
Alternatively, you can gang together several output buffers from standard CMOS devices to increase the drive capability that way, for example by connecting all six of the available inverters in an 74AHC04 together:. As lower voltage 3. When the gate-driver voltage of the FET is higher than your digital supply, at least a level-shifter will be needed in order to be able to drive the device. One of the simplest level shifters is this:. Here, the gate of the small-signal N-FET is driven by a suitable logic signal and a logic level signal can easily turn this N-FET on and the drain of it is pulled up to the gate-drive power supply, V drive.
So in fact, the output is the logical inverse of the input, but the voltage levels are changed to 0 and V drive. When it drives low, its output resistance is pretty much r dson of the FET. However R up must be significantly higher than r dson otherwise the low-level output voltage would not be close to 0V. This in turn means that the turn-on time which is determined by r dson for a P-FET will be significantly — maybe even an order of magnitude — lower than the turn-off time, which is determined by R up.
This imbalance complicates shoot-through protection quite a bit and makes it very hard to turn the driven power FET off fast enough. To overcome this problem, an complementer driver stage can be added between the level shifter and the power-FET:. This stage will make both the high- and low-level drive strength roughly equal, consequently making the turn-on and —off times much closer to one another.
This configuration present some complications: P-MOS transistors are open non-conducting when their gate is at close to the same potential as their source, and closed conducting when the gate is at a significantly lower potential, -5…V lower. That way, the high-level output voltage will be V bat , which will turn the P-FET off properly, and the low-level output voltage will be 0, that is almost always enough to turn the FET on.
You might have problems with extremely low V bat voltages, where you would have to drive the gate to a negative voltage to turn the FET on properly. This however is a rare enough case to ignore simply because high-current H-bridges usually operate at higher voltages and low-voltage H-bridges have low-enough currents that a small logic-level FET can be used in them that can be turned on by -V bat.
This is a very serious limitation as most bridges but the smallest ones operate from higher voltages to maximize power delivery without requiring enormous currents. With all that, for small motors this approach can result in a good, cheap solution. Getting out of this region will very quickly destroy the FET. It can go only as low as — say — V bat V to allow for some safety margin as well.
This is usually accomplished by adding a Zener diode to the drive circuit:. If you set the Zener voltage to about 15V, it will limit your voltage difference between the output and V bat to be within the safe limits. Similar limitations are needed on the low-side as well, if your driver works from V bat and not from a separate power supply.
With all the complexities of level-shifting and voltage-limiting, P-MOS drivers are still simpler than drivers for an N-channel device. The reason is the following: The source of an N-channel device on the high-side has to be connected to the motor terminal and its drain to the power supply, otherwise the body-diode would be forward-biased and would always conduct.
To turn off an N-MOS device in that configuration, you can connect the gate to ground or to the source: gate-source voltage is going to be below or equal to 0. But where to connect the gate to turn on the device? As the drain is connected to power, the source will be at that level as well, but than gate should be higher than that to keep the device on.
As V bat is usually the highest voltage directly available in a system, this voltage needs to be generated. In most cases some kind of a charge-pump is used for that generation, mostly in a boot-strapped configuration:.
While actual implementations could be quite a bit more complex, I will use this simplified variant to explain how things work. The lower leg of it is connected to the middle terminal of the bridge, or more importantly to the source of the power FET it drives, Q1. We close Q2 for some portion of every cycle, and Q1 for the rest not counting shoot-through protection for a minute.
For the part of the cycle, when Q2 conducts, the output terminal voltage V out is 0V, or very close to it. Since one side of C boot is connected to this node, it is also grounded.
D boot , which is connected between V cc and the other side of C boot will make sure that C boot is charged up to V cc :. This of course also means that V boot is equal to V cc , 12V in our example. When it comes to turning Q2 off, V out starts floating. Depending on what the motor, and the other side of the bridge does, either D1 or D2 will open and continue conducting the motor current.
Normally, C boot would discharge quickly towards V cc , but in our case D boot closes and lets V boot rise as high as it wishes:. If we wanted to turn Q1 on at this point, we can still do it: the high-level output voltage of the driver V boot is 12V higher than the source voltage of Q1, as it is connected to V out. All in all, C boot and D boot will make sure that V boot is always at a higher voltage than V out by V cc. Reply 7 months ago. Question 9 months ago. I would like to controll it all by a Teensy 4.
Reply 8 months ago. Yes, you can. You need to change some component values. Which is the better idea to go with, for dc geared brushed motor. Reply 1 year ago. Question 1 year ago on Step 6. Answer 1 year ago. As you see some track are not completely covered by solder mask. They are high current carring tracks. More by the author:.
By Hesam Moshiri, hesam. C] Assembly and Test Figure 8 shows the assembled unit and figure 9 shows the testing environment. Did you make this project? Share it with us! I Made It! Remote Control Light Switch by alanmerritt in Arduino. JuniorV44 5 days ago. Reply Upvote.
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